1. Field of the Invention
This invention relates to converter circuits and more specifically to a control circuit for reducing the dead time between conduction of high side and low side FETs in such circuit.
2. Description of the Related Art
In DC to DC conversion, “good converters” are measured according to the converter efficiency. Efficiency is determined in accordance with fewest power losses in the converters, such as switching losses and losses due to the Power Device's ON resistance.
Synchronous rectifiers are commonly used to reduce switching losses, despite their control complexity. In synchronous rectifiers, one of the main contributors of the power losses is the delay between the control of a high-side/control transistor and the low side/synchronous transistor.
FIG. 1 illustrates a well-known high-speed synchronous buck converter circuit 10. The circuit 10 includes a switching stage having a high side or control Power Device Q1 and a low side or synchronous Power Device Q2 coupled at a switching node. The switching stage receives an input D-C voltage VIN and provides a highly controlled output D-C voltage V0 at an output node. The circuit 10 has an input capacitor C1 parallel connected with the switching stage, an output inductor L connected between the switching node and the output node, and an output capacitor C2 connected to the output node having the output D-C voltage V0. A load is parallel connected with the output capacitor C2.
The Power Devices Q1 and Q2 are turned ON and OFF as usual with pulse width modulation (PWM), so the control Power Device Q1 is ON for a given time while Power Device Q2 is OFF and, Power Device Q2 turns ON when Power Device Q1 turns OFF. The pulse width modulation is controlled to maintain a predetermined output voltage V0 at the output node even though VIN, which may be supplied by a battery in a portable electronics device, varies with age, temperature, power demand, etc.
Care must be taken to prevent simultaneous turn ON of the Power Devices Q1 and Q2, which would create a short circuit across the input circuit. Thus, as illustrated in FIG. 2, a certain dead time is always provided during which both Power Devices Q1 and Q2 are OFF. It is desirable to reduce this dead time as much as possible, preferably to zero to increase the circuit efficiency.
Previous attempts to control the dead time include a fixed delay method illustrated in FIG. 3. Here, the optimum delay, when Power Devices Q1 and Q2 are OFF, can be changed depending on the load, line, and Power Device. The dead time itself cannot be adjusted to achieve the optimum delay per given conditions.
An adaptive control method, illustrated in FIG. 4, is a better control scheme than the fixed delay scheme but it does not adjust itself to the changes on load, line & temperature.
A predictive control scheme illustrated in FIG. 5, monitors a voltage VSW at a switching node connecting the Power Devices Q1 and Q2 and continuously adjusts the delay until it achieves the predetermined value. In this approach, voltage VSW must go below the ground voltage and is compared to a fixed voltage. The voltage VSW going negative just enough to create an optimum delay for a minimum power loss. Due to VSW comparator delay, this approach does not achieve optimum dead time.